Senior DFT Architect

5 days ago

Cochin, Kerala, India beBeeDft Full time ₹ 19,97,500 - ₹ 25,19,900
Lead DFT Engineer Position

The successful candidate will hold a leadership role in driving the development and implementation of Design for Test (DFT) strategies and architectures for high-performance System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.

  • Develop and drive DFT strategies and architectures for complex SoCs and ASICs.
  • Implement and verify DFT features such as scan insertion, compression, automatic test pattern generation (ATPG), memory built-in self-test (MBIST), boundary scan, and IJTAG.
  • Manage the end-to-end DFT flow from register-transfer level (RTL) to gate-level netlist and silicon bring-up.
  • Collaborate with cross-functional teams for seamless integration and yield optimization.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure, and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on automated test equipment (ATE), and yield optimization.
Requirements

Candidates should possess:

  • A Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI Design.
  • At least 7 years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
  • Strong knowledge of RTL design, static timing analysis (STA), and synthesis flows.
  • Proficiency in scripting languages (Python, Perl, Tcl) for flow automation.

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