Senior DFT Engineer Position

Lead DFT Engineer PositionThe successful candidate will hold a leadership role in driving the development and implementation of Design for Test (DFT) strategies and architectures for high-performance System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.Develop and drive DFT strategies and architectures for complex SoCs and...

Key Responsibilities:We are seeking an experienced DFT Engineer to drive design for test architecture definition and implementation for complex SoCs. This role involves planning, executing, and delivering scan, ATPG, MBIST, and boundary scan insertion and validation.You will work closely with EDA vendors to evaluate, deploy, and optimize DFT tool flows....

Unlock the Power of DFT EngineeringDirector Applications Engineering Role OverviewAs a senior leader in the field of DFT engineering, you will drive innovation and growth by leading cross-functional teams focused on delivering advanced DFT solutions.You will define strategic initiatives to increase market presence and customer success through effective...

Are you a seasoned DFT expert looking for a challenging role?About the JobWe're seeking a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs.This technical leader will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon...

Key Highlights:In depth knowledge of DFT conceptsExperience in RTL and Gate level simulations of scan and MBIST test vectorsKnowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax)Job Description:DFT Lead - 7 to 15 Years. Responsible for defining and implementing DFT strategies for complex digital...

STA EngineerWe are seeking an experienced STA Engineer to join our backend implementation team.The ideal candidate will have a strong background in RTL-to-GDSII implementation, with expertise in performance, power, and area (PPA) optimization and signoff closure.Key Responsibilities:Timing Closure Fundamentals: The successful candidate will have a deep...

Key Responsibilities:- Define and implement DFT architecture for SoCs and IPs.- Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG).- Work with RTL designers to insert DFT logic and resolve DRC violations.- Generate and validate test patterns using tools such as TetraMAX, FastScan, DFT Advisor, etc.- Analyze and improve fault...

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX, FastScan, DFT Advisor, etc. Analyze and improve fault coverage...

Key Responsibilities:Define and implement DFT architecture for SoCs and IPs.Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG).Work with RTL designers to insert DFT logic and resolve DRC violations.Generate and validate test patterns using tools such as TetraMAX, FastScan, DFT Advisor, etc.Analyze and improve fault coverage and...

We are seeking a highly skilled and motivated Senior IC Architect to lead the overall chip architecture and design execution. This individual will be responsible for overseeing the entire design process, from RTL freeze to GDSII delivery.Key ResponsibilitiesOwns multi-block design integrationManages handoff and sign-off of key stages: RTL freeze, synthesis,...