Senior DFT Architect

15 hours ago

Cochin, Kerala, India beBeeDesign Full time ₹ 20,00,000 - ₹ 25,00,000

Key Responsibilities:

We are seeking an experienced DFT Engineer to drive design for test architecture definition and implementation for complex SoCs. This role involves planning, executing, and delivering scan, ATPG, MBIST, and boundary scan insertion and validation.

You will work closely with EDA vendors to evaluate, deploy, and optimize DFT tool flows. Automating repetitive tasks using scripting will improve efficiency and reduce errors. You will also support test vector generation and validation for ATE.

In addition, you will provide technical guidance and mentorship to junior engineers in the DFT team.

**Requirements:**

3+ years of experience in DFT architectures and methodologies, including but not limited to:

  • Scan Insertion & Verification
  • ATPG (Automatic Test Pattern Generation)
  • MBIST (Memory Built-In Self-Test)
  • JTAG / Boundary Scan

Hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).

Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.

Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.

Experience collaborating with RTL designers, verification engineers, and physical design teams to ensure seamless DFT integration.

Strong problem-solving skills, ability to debug complex test issues, and deliver high-quality DFT solutions within tight schedules.

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