
Senior/Lead STA Design Specialist
2 days ago
We are seeking a skilled Static Timing Analysis (STA) Engineer to own and drive timing closure for complex System-on-Chip (SoC) designs across multiple technology nodes.
- Owning and driving timing closure for complex SoC and ASIC designs
- Performing full-chip and block-level timing analysis using industry-standard tools
- Collaborating with RTL, synthesis, physical design, and verification teams to resolve timing violations
- Developing and maintaining timing constraints, running STA checks, and supporting ECO timing closure
- Contributing to methodology improvements and timing signoff strategies
- Reporting timing status, risks, and closure plans to technical leads and project stakeholders
Required Skills & Experience:
- 5–10 years of solid hands-on experience in STA and timing closure
- Strong expertise in timing concepts, constraints development, and signoff methodology
- Proficient in tools like Synopsys Primetime, Cadence Tempus
- Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis
- Good scripting skills to automate and debug flows
- Experience with advanced nodes is a plus
- Strong analytical, problem-solving, and communication skills
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