Lead Static Timing Analysis

Job DescriptionHand-on experience and Comprehensive knowledge of Static Timing Analysis.Hands-on experience in Logical aware Synthesis, Logical Equivalence check and, Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge in the Timing closure on Sub-system level & Block level and Chip level.Knowledge in writing Manual ECOs to...

Static Timing Analysis (STA) Lead Location: Bangalore, KAExperience: 7–18 YearsBudget: Up to 30 LPA (DoE)Industry: Semiconductors | ASIC | SoC | AI/Networking ChipsJob Type: Full-Time Job Overview We are seeking a highly skilled Static Timing Analysis (STA) Lead to drive timing closure for large-scale, high-performance ASIC/SoC designs. The ideal candidate...

Static Timing Analysis (STA) LeadLocation: Bangalore, KAExperience: 7–18 YearsBudget: Up to 30 LPA (DoE)Industry: Semiconductors | ASIC | SoC | AI/Networking ChipsJob Type: Full-TimeJob OverviewWe are seeking a highly skilled Static Timing Analysis (STA) Lead to drive timing closure for large-scale, high-performance ASIC/SoC designs. The ideal candidate...

Static Timing Analysis (STA) Engineer Job DescriptionJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with...

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.Key Responsibilities:Own...

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.Key Responsibilities:Own...

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The...

Key Skills: Static Timing Analysis,PrimeTime Roles and Responsibilities: Conduct block-level and full-chip static timing analysis across all phases of development. Develop timing methodologies and infrastructure from RTL synthesis to timing closure. Collaborate with architects and designers to define block and chip-level timing constraints. Define analysis...

Key Skills: Static Timing Analysis,PrimeTimeRoles and Responsibilities:Conduct block-level and full-chip static timing analysis across all phases of development.Develop timing methodologies and infrastructure from RTL synthesis to timing closure.Collaborate with architects and designers to define block and chip-level timing constraints.Define analysis...

Static Timing Analysis (STA) Engineer Job DescriptionJob Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating...