Static Timing Analysis

Static Timing Analysis (STA) EngineerJob Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...

Static Timing Analysis (STA) Engineer Job DescriptionJob SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with...

Hi Folks,Please find here JD for your reference.Work Location: BangaloreStatic Timing Analysis Engineer – Exp 8 yrs and higher.Job description :1.    STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.2.    Timing analysis, validation and debug across multiple PVT conditions using Tempus or Primetime at chip...

Experience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...

Description : Job Title : STA Engineer Location : Bangalore, India Experience : 4 yearsJob Overview : We are seeking a highly skilled Design Verification and Static Timing Analysis (STA) Engineer with expertise in scan, ATPG, and SV UVM methodologies, as well as pre- and post-layout STA. The ideal candidate will be responsible for ensuring the...

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Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.8 years of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology growth...

We're Hiring – STA Engineer (Tempus Experience)|#BangaloreJoinMirafra Technologies, a leading name inVLSI design and innovation, and be part of a dynamic engineering team Position:STA EngineerExperience:4+ YearsLocation:BangaloreKey Skills & Responsibilities:Strong working knowledge of Synthesis, LEC, and STA concepts.Hands-on experience in block-level...

SDC and constraints syntaxTiming signoff tools like Primetime / Tempus is a mustMMMC, DMSA or TweakerBlock /SOC,AOCV/POCV, TCL / Perl.

LTTS is looking for STA engineers with 5+ Years of experience, Detailed JD is mentioned below :: • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. • Work with partitions/block owner to give timing ECO for...