SoC Static Timing Analysis Engineer, Silicon

2 days ago

Bengaluru, Karnataka, India Google Full time ₹ 20,00,000 - ₹ 25,00,000 per year
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology growth and platform development kit (PDK) changes.
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
  • Experience with a scripting language like Perl or Python.
  • Experience in developing constraints and validating using Timing Constraints Manager (e.g., Synopsys) or TimeVision (e.g., Ausdia).
About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will design and build the systems that are important for computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. You will be the part of Google's Silicon team, developing hardware and software to enable Google's innovations in working with Application Specific Integrated Circuits (ASIC). You will drive the complete design constraints development, its validation, working on sign-off timing convergence for designs including deciding the initial timing goals, setting up the timing analysis flows and methodology, and working with the implementation engineers to achieve the timing goals.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities
  • Design constraints creation from architecture/microarchitecture documents with an understanding of various external Input Output (IO) protocols.
  • Design constraints validation across multiple corners/modes using Fishtail/Timevision.
  • Run Primetime and validate constraints post synthesis runs. Set up timing constraints, defining the overall static timing analysis (STA) methodology.
  • Work with the design team and block owners throughout the project for sign-off timing convergence. Work on constraints promotion and demotion flow using fishtail, timevision.
  • Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA or tools for methodology development.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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