RTL Verification Engineer: 5G Radio

5 months ago


Bengaluru, India Mavenir Full time
Role Summary

FPGA Design and Verification Engineer for Board Management and Low PHY functional blocks you will join the Radio Development team for developing high end OpenRAN 5G and mMIMO RRUs.

Key Responsibilities

Write test bench from scratch/ modify the existing to meet IP verification requirement.
Verification of 5G Radio RTL modules/ SOC in Questasim SV-UVM/ Vivado environment.
Processor and FPGA (PS/PL) co-simulation to meet today’s SOC verification requirement.
Creating VIP/ using third party VIP/ using Xilinx C model for various RTL functionalities.
Making test plan/test cases, automate test case execution.
Reporting test results and quality metrics.
Work closely with designer for IP integration, testing and debugging.

Job Requirements

  • Minimum 3 years of working experience in RTL verification.
  • Proficiency in System Verilog and experience in UVM.
  • Knowledge in ORAN protocol/DDR4, DMA, AXI interfaces.
  • Familiarity in wireless communication concepts, signal processing concepts FFT/DUC/CFR/DPD/PRACH.
  • Understanding in ORAN and 5G 3GPP standards.
  • Experience in Questasim tool flow.
  • Scripting experience for verification automation.
  • BE/B.Tech/M.E/M.Tech in Electronics & communication/VLSI or equivalent is preferred.



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