RTL Verification Engineer for 5G Radio Development

4 weeks ago


Bengaluru, Karnataka, India Mavenir Full time

Role Summary

Mavenir is seeking a skilled FPGA Design and Verification Engineer to join our Radio Development team for developing high-end OpenRAN 5G and mMIMO RRUs. The ideal candidate will have a strong background in RTL verification and experience with System Verilog and UVM.

Key Responsibilities

  • Design and verify RTL modules for 5G Radio systems using Questasim SV-UVM and Vivado environments.
  • Collaborate with designers to integrate and test IP blocks.
  • Develop and maintain test plans, test cases, and automation scripts.
  • Work closely with the team to ensure high-quality results and meet project deadlines.

Requirements

  • Minimum 3 years of experience in RTL verification.
  • Proficiency in System Verilog and UVM.
  • Knowledge of ORAN protocol, DDR4, DMA, AXI interfaces, and wireless communication concepts.
  • Experience with Questasim tool flow and scripting for verification automation.
  • BE/B.Tech/M.E/M.Tech in Electronics & Communication/VLSI or equivalent.


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