RTL Verification Engineer: 5G Radio Solutions

3 weeks ago


Bengaluru, Karnataka, India Mavenir Full time
Role Overview

FPGA Design and Verification Engineer for Board Management and Low PHY functional blocks are required to join the Radio Development team at Mavenir for developing high-end OpenRAN 5G and mMIMO RRUs.

Key Responsibilities

Key responsibilities include writing test benches from scratch or modifying existing ones to meet IP verification requirements, as well as verifying 5G Radio RTL modules and SOC in Questasim SV-UVM and Vivado environments.

Processor and FPGA (PS/PL) co-simulation is also required to meet today's SOC verification requirements. Additionally, creating VIP or using third-party VIP or Xilinx C models for various RTL functionalities is necessary. Making test plans, test cases, and automating test case execution, as well as reporting test results and quality metrics, are also essential tasks.

Requirements

  • Minimum 3 years of experience in RTL verification
  • Proficiency in System Verilog and experience in UVM
  • Knowledge of ORAN protocol, DDR4, DMA, AXI interfaces
  • Familiarity with wireless communication concepts, signal processing concepts FFT, DUC, CFR, DPD, PRACH
  • Understanding of ORAN and 5G 3GPP standards
  • Experience in Questasim tool flow
  • Scripting experience for verification automation
  • BE/B.Tech/M.E/M.Tech in Electronics & Communication/VLSI or equivalent is preferred


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