RTL Design Engineer

1 month ago


Bengaluru, Karnataka, India UST Full time
Job Summary

UST is seeking a highly skilled RTL Design Engineer to join our team. As a key member of our design team, you will be responsible for designing and implementing complex digital circuits using RTL languages such as VHDL and Verilog.

Key Responsibilities
  • Collaborate with chip architects to understand architecture concepts and high-level requirements.
  • Convert chip specifications to RTL using internal and external IPs.
  • Plan and deliver RTL for continuous integration testing.
  • Support the verification team in devising appropriate test plans and verification strategies.
Requirements
  • Experience in ASIC/SoC front-end design and methodologies, preferably with RTL Verilog and VHDL-based design.
  • Previous experience with SoC integration, processor-based architectures, and low-power design is highly desirable.
  • Self-driven and capable of independent work and decision-making.
  • Knowledge of frontend design experience on IPs involving processor-based subsystems, serial standard interfaces, and memory controllers.
  • Exposure to system security and hands-on front-end design of complex multi-clock domain blocks.
  • Fluency in design and verification languages such as VHDL, Verilog, C, and System Verilog.
  • Experience with Spyglass for lint and CDC checks, synthesis, and LEC flow.
  • Ability to identify and implement complex ECOs in netlists and define and debug timing constraints.
  • Knowledge of verification methodologies to actively participate in debug analysis.
  • Knowledge of system-level flows and interaction with firmware and software is an added advantage.


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