RTL Verification Engineer for 5G Radio Development
3 days ago
FPGA Design and Verification Engineer for Board Management and Low PHY functional blocks will join the Radio Development team for developing high-end OpenRAN 5G and mMIMO RRUs.
Key Responsibilities
Create test benches from scratch or modify existing ones to meet IP verification requirements.
Verify 5G Radio RTL modules and SOC in Questasim SV-UVM and Vivado environments.
Perform processor and FPGA (PS/PL) co-simulation to meet today's SOC verification requirements.
Develop VIP or use third-party VIP or Xilinx C models for various RTL functionalities.
Develop test plans, test cases, automate test case execution, and report test results and quality metrics.
Work closely with designers for IP integration, testing, and debugging.
Requirements
- Minimum 3 years of experience in RTL verification.
- Proficiency in System Verilog and experience in UVM.
- Knowledge of ORAN protocol, DDR4, DMA, AXI interfaces.
- Familiarity with wireless communication concepts, signal processing concepts FFT/DUC/CFR/DPD/PRACH.
- Understanding of ORAN and 5G 3GPP standards.
- Experience in Questasim tool flow.
- Scripting experience for verification automation.
- BE/B.Tech/M.E/M.Tech in Electronics & communication/VLSI or equivalent is preferred.
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