Senior RTL/FPGA Design Engineer

Overview

Azista is a passionate business enterprise with an aim to add value and provide services in various verticals like Food, Medical Devices, Healthcare Products, Aerospace, Innovative Composites, Earth Observatory Satellites. We are renowned manufacturers of healthy food products, Pharma, innovative and cost-efficient composites, Satellites communication systems, which required for today era of world markets. We offer the best-in-class services at affordable prices to improve the quality of living.

Role:
Senior RTL/FPGA Design Engineer — Satellite Sub-systems

Location:
Hyderabad

Education:
B.E./B.Tech in Electronics & Communication (or equivalent)

Experience:
2–6 years

Role Summary

Design, implement, and verify FPGA-based RTL for satellite sub-systems. Own the full FPGA flow—from architecture input and micro-architecture to RTL, verification, synthesis/implementation, and on-board validation—working closely with system, hardware, and embedded software teams to deliver high-performance, reliable designs for space environments.

Responsibilities:

System & Architecture

• Contribute to DSP, system, and board-level architecture for satellite sub-systems.
• Partition algorithms across FPGA and software; identify signal-processing blocks and control paths.
• Estimate device resources, compute/memory bandwidth; collaborate with PCB teams on pinout and interfaces.

RTL Design & Verification

• Develop optimized RTL in VHDL/Verilog for high-speed data paths, control/state machines, and interfaces.
• Produce micro-architecture specs, write clean code, and participate in peer/code reviews.
• Perform functional simulation and timing analysis; drive constraints and timing closure.

Implementation & Bring-Up

• Synthesize and implement designs in Xilinx flows (e.g., Vivado); integrate/customize IP.
• Execute board-level testing and debug using JTAG, logic analyzers, and oscilloscopes.
• Support subsystem integration at test facilities; analyse issues and deliver fixes.

Documentation & Compliance

• Create and maintain SRS, micro-architecture docs, test plans, ATPs, analysis and validation reports.
• Participate in design and readiness reviews; follow aerospace documentation rigor.

Core Skills (Must-Have)

• Strong
  VHDL
  (plus working Verilog) for RTL design.
• Xilinx FPGA toolchain: synthesis, P&R, constraints, timing closure (
  Vivado
  ).
• Functional/timing simulation and testbench practices.
• Board-level debug and lab validation skills.
• Interfaces and buses:
  PCIe, Ethernet, UART, SPI
  ; familiarity with multi-gigabit transceivers (
  MGT/MGTY
  ).
• Version control (Git; SVN exposure acceptable).
• Clear technical communication and documentation.

Domain & Nice-to-Have

• Memory subsystem & data movement:
  DDR/SDRAM/LPDDR, BRAM/URAM controllers; AXI/AXI4-Stream/Avalon; DMA engines; ping-pong/double buffering; arbitration; throughput/latency tuning; deterministic read/write paths for payload data.
• Bad-data detection & management (space):
  ECC/EDAC, CRC/parity, memory scrubbing, SEU/SET mitigation (e.g., TMR, Hamming), timeout/retry FSMs, watchdogs, fault logging/telemetry, FDIR strategies, memory BIST/BISR; familiarity with NV memories (NOR/NAND/FRAM/MRAM) and wear-leveling.
• Implementing
  DSP algorithms
  on FPGAs for aerospace/satellite applications.
• Modeling in
  MATLAB/Octave
  ; test-vector generation and data visualization.
• Fixed-point conversion of floating-point algorithms for FPGA efficiency.
• Familiarity with Xilinx DSP IPs (
  FFT, FIR, DDC, NCO
  , etc.).
• ADC/DAC interfacing and performance analysis.
• High-speed data movement over
  PCIe/Ethernet
  using MGTs.
• System Verilog/SystemC exposure; structured verification methods.
• Experience producing
  SRS/ATP
  and maintaining comprehensive design records.

Tools & Technologies

• HDLs:
  VHDL, Verilog (System Verilog/SystemC a plus)
• FPGA Tools:
  Xilinx Vivado; timing/simulation tools
• Lab:
  JTAG, logic analyser, oscilloscope
• Modelling:
  MATLAB/Octave
• Version Control:
  Git (SVN acceptable)