Engineer - RTL

Position:RTL Design EngineerExperience:5 - 8 YearsQualifications:BE/Btech in ECE/EEEResponsibilitiesThe candidate should have strong RTL design experience.Strong design experience in Ethernet IPs or Ethernet protocol domain.Knowledge in Verilog/VHDL languagesScripting languages: TCL/Perl/Python (any one).Knowledge of AXI Protocols.

Exp Level : More than 5+Years will be consideredCompany DescriptionNG-RAN IIT Hyderabad is at the forefront of global wireless innovation, prominently contributing to the development of 5G technologies. The institute's team, alongside academic and industry partners, submitted more than 400 technical papers to 3GPP workgroups from 2017 to 2021, resulting in...

Job Requirements Job Title: RTL Tech Lead We are currently seeking a highly skilled and experienced RTL Tech Lead to join our team. As the RTL Tech Lead, you will be responsible for leading the development and implementation of RTL designs for our projects. You will work closely with the engineering team to ensure the successful delivery of high-quality...

Job Title: RTL Design EngineersExp Level: 4+ yrsLoctaion: Hyderabad /BangaloreJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

7+years of experience in RTL design and verification.Proven experience with digital logic design using Verilog, VHDL, or System Verilog.Experience with simulation tools such as VCS, QuestaSim, or similar.Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus).Develop RTL code based on system-level specifications using...

Role : ASIC RTL Engineer / Digital DesignLocation: Bangalore, Hyderabad, PuneMandatory SkillRTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro ArchitecturePCIe/DDR/Ethernet - Any OneI2C,UART/SPI - Any OneSpyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any OneScripting languages like Make flow, Perl ,shell, python - Any OneGood To...

RTL (ASIC) Design EngineerExperience : 1-3 YearsLocation : HyderabadInterested,please share your updated resume to

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity...

Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences - from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create...