Senior Design Verification Engineer

2 days ago

Hyderabad, Telangana, India NG-RAN IIT Hyderabad Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Company Description

NG-RAN IIT Hyderabad is renowned for leading India's contributions to 5G global wireless standards, submitting over 400 technical papers to 3GPP work groups from 2017 to 2021. The team has developed several 5G standard-essential patents, including the innovative "pi/2 BPSK with spectrum shaping" technology. With funding from DoT and MeitY, IITH successfully developed prototypes for 5G base stations, user equipment, and NB-IoT System-on-Chip. WiSig Networks Pvt Ltd, a start-up at IITH's technology incubator, is commercializing these IPs and products. As India looks toward 6G technology, NG-RAN IIT Hyderabad plays a crucial role in defining future wireless standards.

Role Description

This is a full-time on-site role for an RTL Design and Verification Engineer located in Hyderabad. The engineer will be responsible for creating and verifying RTL designs, performing formal and functional verification, and debugging designs to ensure they meet specified requirements. Daily tasks include collaborating with cross-functional teams, developing design specifications, and validating design performance.

Exp Level :4+Years

Responsibilities:

  • Architecture exploration and Micro-architecture development
  • RTL design and integration for 
    5G NR UE
    systems using 
    Verilog/System Verilog
  • Collaboration with multi-discipline teams to integrate, test and debug the designs on FPGAs

Required Qualifications:

  • Master's/Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or equivalent practical experience

Skills/Experience Required

  • Strong Domain Knowledge on RTL Design, implementation, and integration for FPGA based designs.
  • Experience with RTL coding using 
    Verilog/System Verilog.
  • Proficiency in complete FPGA design flow
    .
  • Experience with protocols like 
    AXI4-stream
     and 
    AXI4
    .
  • Exposure in scripting (Python/TCL).
  • Strong debugging capabilities at RTL simulation and FPGA Emulation.
  • Proficiency in version control tools like 
    GIT
    .

Preferred Experience

  • Experience with 
    Intel
     or 
    Xilinx
     FPGAs, especially MPSoC FPGAs
  • Experience in Fixed-point arithmetic implementation in Verilog
  • Experience with high-speed serial communication IPs on FPGAs
  • Experience in implementing DSP algorithms
  • RTL Development for wireless communication systems 
    (Most preferably 5G NR)

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