RTL Verification

2 days ago

Hyderabad, Telangana, India Canvendor Full time ₹ 12,00,000 - ₹ 36,00,000 per year
Role Overview: You will be responsible for RTL verification and developing SV/UVM testbenches at Top/Sub-system/Block-levels. Your role will involve driving test plan and test spec development, executing tests, and generating relevant documents. Additionally, you will contribute to verification environment architecture and methodology development. The position requires experience in System Verilog, UVM programming, and verification of protocols like Ethernet, PCIe, SPI, I2C, and USB. Strong debugging skills, familiarity with Xilinx technology, FPGA verification, and scripting languages like Perl, Python, or TCL are also essential for this role. Key Responsibilities: - Develop SV/UVM testbenches at Top/Sub-system/Block-levels - Drive test plan and test spec development and execution - Generate documents such as user-guide, test plan, test spec, and test report - Contribute to verification environment architecture and methodology development - Verify protocols like Ethernet, PCIe, SPI, I2C, and USB - Perform HW testing and work with test equipment like logic and traffic analyzers, test generators, etc. - Utilize Xilinx technology and tools for FPGA verification and testing - Demonstrate strong debugging skills at device and board level - Use scripting languages such as Perl, Python, or TCL Qualifications Required: - 5+ years of experience in RTL verification - Proficiency in System Verilog and UVM programming - Experience with Xilinx technology, FPGA verification, and testing - Familiarity with verification of protocols like Ethernet, PCIe, SPI, I2C, and USB - Strong debugging skills at device and board level - Scripting language experience in Perl, Python, or TCL - Excellent interpersonal, written, and verbal communication skills - Problem-solving and analytical skills Please note that immediate joiners are preferred for this position. If you are interested in this opportunity, kindly share your updated CV with hidden_email.,

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