RTL Design Engineer

Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

Position:RTL Design EngineerExperience:5 - 8 YearsQualifications:BE/Btech in ECE/EEEResponsibilitiesThe candidate should have strong RTL design experience.Strong design experience in Ethernet IPs or Ethernet protocol domain.Knowledge in Verilog/VHDL languagesScripting languages: TCL/Perl/Python (any one).Knowledge of AXI Protocols.

Exp Level : More than 5+Years will be consideredCompany DescriptionNG-RAN IIT Hyderabad is at the forefront of global wireless innovation, prominently contributing to the development of 5G technologies. The institute's team, alongside academic and industry partners, submitted more than 400 technical papers to 3GPP workgroups from 2017 to 2021, resulting in...

Position: RTL Design EngineerExperience: 5 - 8 YearsQualifications: BE/Btech in ECE/EEEResponsibilities -The candidate should have strong RTL design experience.Strong design experience in Ethernet IPs or Ethernet protocol domain.Knowledge in Verilog/VHDL languagesScripting languages: TCL/Perl/Python (any one).Knowledge of AXI Protocols.

Job Requirements he RTL Design Engineer is responsible for designing and implementing digital circuits using Hardware Description Languages (HDL) such as Verilog or VHDL.They work on creating logic at the Register Transfer Level (RTL) and collaborate with verification, synthesis, and physical design teams.Key Responsibilities:Understand and analyze design...

Hi All,Job Title - RTL Design EngineersExp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity...

Looking for your next big challenge in ASIC Design?We're hiringASIC Design Engineers with8–15 yearsof experience to join our team inHyderabadIf you have expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure, and have completed at least one tape-out cycle, we'd love to connect with you. Location: Hyderabad Experience: 8–15...

Job Requirements Job Title: RTL Tech Lead We are currently seeking a highly skilled and experienced RTL Tech Lead to join our team. As the RTL Tech Lead, you will be responsible for leading the development and implementation of RTL designs for our projects. You will work closely with the engineering team to ensure the successful delivery of high-quality...