RTL Design Engineer

Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

Position: RTL Design EngineerExperience: 5 - 8 YearsQualifications: BE/Btech in ECE/EEEResponsibilities -The candidate should have strong RTL design experience.Strong design experience in Ethernet IPs or Ethernet protocol domain.Knowledge in Verilog/VHDL languagesScripting languages: TCL/Perl/Python (any one).Knowledge of AXI Protocols.

Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

Position: Senior ASIC RTL Design EngineerExperience: 10+ YearsLocation: HyderabadWork Mode: Work From OfficeJob Description:We are seeking a highly skilled Senior ASIC RTL Design Engineer with strong expertise in Verilog/SystemVerilog RTL coding and deep knowledge of digital design concepts. The ideal candidate must demonstrate excellent debugging skills and...

About UsWe are a dynamic team of young engineers, domain experts, and seasoned sales professionals dedicated to providing comprehensive turnkey solutions for complex challenges in Signal Processing. Our expertise spans the cutting-edge technologies in Signal Processing, addressing critical needs in the Defence and Aerospace sectors. Our offerings encompass a...

Position:RTL Design EngineerExperience:5 - 8 YearsQualifications:BE/Btech in ECE/EEEResponsibilitiesThe candidate should have strong RTL design experience.Strong design experience in Ethernet IPs or Ethernet protocol domain.Knowledge in Verilog/VHDL languagesScripting languages: TCL/Perl/Python (any one).Knowledge of AXI Protocols.

Title: RTL/Vivado DesignerWork Location: HYDERABADExperience: 4+ YearsNotice Period: 15 Days (Max)RTL/Vivado DesignerREQUIRED SKILLS:Candidate should have 4+ years of experience in HW debuggingShould have hands on experience in Vivado ToolNeed to work on Datasheet and other documents, should have good communication skill.Knowledge on different interfaces...

Hello EveryoneWe are seeking RTL Design Engineer with 3- 4 Years of Experience for the Position in Hyderabad.Candidates who can start immediate or within 15 Days are preferred*.Interested individuals or referrals can share profile with us.Qualifications: B.Tech/B.E/M.Tech/M.EBelow the JD:-CDC, RDC runs for complex SOC design. analysis, debugDesign...

Exp Level : More than 5+Years will be consideredCompany DescriptionNG-RAN IIT Hyderabad is at the forefront of global wireless innovation, prominently contributing to the development of 5G technologies. The institute's team, alongside academic and industry partners, submitted more than 400 technical papers to 3GPP workgroups from 2017 to 2021, resulting in...

My name is Shahid I am reaching out with a role that fits engineers who enjoy real ownership, from shaping micro-architecture to watching their RTL come alive in silicon. If you’re looking for a space where your design decisions actually matter, this one is worth your time.Job Title - Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem) Location...