Vlsi - Static Timing Analysis

**VLSI - Static Timing Analysis - Freelancers/Consultant Trainer**:
**About Cranes Varsity**:
Cranes Varsity is a pioneer Technical Training institute turned EdTech Platform offering Technology educational services for over 24 years. Being a trusted partner of over 5000+ reputed Academia, Corporate & Defence Organizations we have successfully trained 1 Lakh+ engineers and placed 70,000+ engineers. Cranes Varsity offers high-impact hands-on technology training to Graduates, Universities, Working Professionals, and the Corporate & Defence sectors.

**Job Title**: VLSI - Static Timing Analysis

**Position -** Trainer

**Duration: 10 Days**

**Department - Training**

**Experience -** Minimum 8 Years - 15 Years of EdTech/IT/Corporate/Institutions etc

**Education -**Should have completed Degree in BTECH

**Tools Required**:Licensed version - Synopsis/Cadence tools (SpyGlass Lint, SpyGlass CDC, Design Compiler, Prime Time)

Software tools required Synopsis/Cadence tools (SpyGlass Lint, SpyGlass CDC, Design Compiler, Prime Time).

Day 1: VLSI Development Flow & EDA Tools (8 hrs) - Topics: - VLSI Technology Overview - IPs, Subsystems, and SoCs - SoC Design Flow: RTL Synthesis PnR STA - EDA Tool Overview - Hands-On: - RTL block inspection walkthrough - Explore tool environment setup (e.g., Synopsys DC)

Day 2: RTL Synthesis - Concepts & Setup (8 hrs) - Topics: - RTL Linting & Clock Domain Crossing (CDC) - Synthesis Basics: Mapping, Constraints - Hands-On: - Run RTL linting (SpyGlass Lint/CDC) - CDC checks on sample modules

Day 4: Introduction to Static Timing Analysis (8 hrs) - Topics: - What is STA? - Setup/Hold, Slack, Skew, Delay Models - Hands-On: - Analyze a synthesized netlist timing report - Visualize timing paths (e.g., setup/hold violations)

Day 5: STA Deep Dive (8 hrs) - Topics: - Path Classification: Launch/Capture - Timing exceptions: False Paths, Multi-cycle Paths - Clock Uncertainty and Jitter - Hands-On: - Add constraints to declare false and multi-cycle paths - Fix timing violations

Day 6: Timing Closure & Reports (8 hrs) - Topics: - Static Timing Reports: Analysis and Fixes - Derating, Clock Gating Checks - Area & Power considerations during STA - Hands-On: - Interpret timing reports - Use constraints to balance area/power/timing

Day 7: EDA Tool Scripting & Automation (8 hrs) - Topics: - Tool flow automation using Tcl scripting - Batch mode synthesis & STA automation - Hands-On: - Create a complete Tcl script for Synthesis + STA - Generate reports via script

Day 10: Project + Review (8 hrs) - Hands-On Project: - Synthesize RTL for a given IP(RISC V Processor) - Perform complete STA - Create synthesis/STA scripts - Review results (area, power, timing).

**Desired Skills and Experience**:

- Negotiation Skills
- Selling to Customer Ne
- edsMotivation for Sales & Target Oriented
- Building Relationships
- Strong written, verbal, analytical and presentation skills.
- Master’s degree/Bachelor’s degree required or equivalent combination of education and experience from which comparable knowledge and abilities can be acquired
- 08Years to 15 years’ experience in a university environment and/or working in development/management organization.
- Outstanding communication and interpersonal skills: This includes presentation/speaking skills and small group facilitation. Exemplary writing and editing skills are required
- Ability to work independently and as part of a team in a fast paced environment
- Strong computing skills, including the ability to self-teach in order to gain mastery systems as well as the ability to train others in systems.

**Job Category**:DEPARTMENT

**Job Type**:Full Time

**Job Location**:Bangalore