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2 days ago
You will be responsible for integrating various internal/external IP into the SoC and providing high quality RTL net list to the Back End team. Be involved in all aspects of SOC uArch/RTL including verification, synthesis, low power, DFT etc. and get creative by defining new flows and methodologies.
Have a prior experience in the thid party IP design & integration of 28nm ,65nm,130nm technologies.
Responsibilities. Responsible for integrating various internal/external IP into the SoC
Implement design quality checks such as Lint, CDC/RDC and UPF
Test and debug of SoC features
Participate in synthesis, timing closure and silicon bringup
Scripting to automate flows
**Requirements.**
Strong fundamentals in digital ASIC design; experience using SystemVerilog. Strong skills in various front end design tools and techniques such as logic equivalence, lint checks, clock and reset domain crossing and DFT
Experience designing with multiple power domains and writing UPF
Knowledge of SOC/CPU architecture. Familiarity with high performance and low power design techniques
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team spread across multiple sites and be productive under aggressive schedules
**Job Types**: Full-time, Permanent
Pay: ₹1,000,000.00 - ₹2,400,000.00 per year
Schedule:
- Day shift
**Experience**:
- total work: 4 years (required)
- SystemVerilog: 4 years (required)
- DFT: 4 years (required)
- SOC/CPU architecture: 4 years (preferred)
Work Location: In person
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