Senior/Lead STA engineer

We’re Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany: ACL Digital CompanyLocation: Bangalore & HyderabadExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you’re an STA expert who thrives in...

Skills Required Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at sub HM/block/top level. Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for...

LTTS is hiring for PD/STA Engineers with 7-10 years of experience.Job Location : BangaloreBelow is the job description...The PD/STA Engineer will be responsible for pre-design and static timing analysis tasks to ensure efficient silicon bring-up and product success. Day-to-day tasks include collaborating with design teams, performing timing analysis, and...

Looking for STA Engineer. Exp.-5+yrs. Job Location- Bangalore/Hyderabad/remote. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Prime time constraint generation/development at Top level, full chip level and clean up. Multimode multi corner timing knowledge and timing closure at...

Technical Skills: Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP level constraint integration. Multi-voltage/Switching aware corner definitions. RC/C model selection understanding. ...

Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

BE /Btech EXp- 5- 12 Yrs Work on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm. • Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR. • Contribute to design methodology, flow automation. • Innovate & implement Power, Performance and Area...

Experience : 5+years Location : Bangalore Job Description: As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages...

Timing analysis is a critical component of our process.We are seeking a skilled engineer to join our team and take on the challenge of performing timing analysis, validation, and debug across multiple PVT conditions using Tempus.The ideal candidate will have experience with Tempus DMMMC flow for STA and be proficient in STA setup, convergence, reviews, and...

STA Engineer Experience : 4-5 years Location : Bangalore Timing closure fundamentals Constraint creation and maintenance exposure DFT modes in STA timing closure Interested,please drop your updated resume to