Static Timing Analysis Leader

3 days ago

Kollam, Kerala, India beBeeTiming Full time ₹ 1,80,00,000 - ₹ 2,20,00,000

Job Opportunity: Static Timing Analysis Lead

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The successful candidate will be responsible for leading static timing analysis efforts for complex systems-on-chip (SoCs). This involves developing prime time constraints at full chip level, multimode multi-corner timing knowledge, and top-level timing closure with sign-off in a specific methodology.

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Key Responsibilities:

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  • ">
  • Netlist and constraint sign-in checks and validation.">
  • Prime time constraint development at full chip level and cleanup.">
  • Multimode multi-corner timing knowledge and timing closure at sub HM/block/top level.">
  • Top-level timing closure with sign-off STA in the specified methodology with Xtalk and OCV.">
  • Top-level ECO implementation strategy development for netlist, RTL, and timing level changes.">
  • Scripting experience in Perl/TCL is required.">
  • Excellent debugging skills are necessary to handle implementation issues and come up with creative solutions.">
  • Expertise in technologies from 28nm and below is mandatory.">
  • A minimum of 8+ years of experience in Synthesis & STA, with timing constraints expertise is required.">
  • Familiarity with Primetime or Tempus is preferred.">
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Requirements:

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  • A good understanding of synthesis and static timing analysis is essential.">
  • Experience with Primetime or Tempus is desirable.">
  • Strong problem-solving skills are necessary.">
  • Ability to work in a team environment is required.">
  • Candidates should be available within 30 days.">
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Benefits:

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  1. ">
  2. Opportunity to work on complex projects.">
  3. Chance to develop leadership skills.">
  4. Collaborative work environment.">
"]},

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