
Senior Static Timing Analysis and Place and Route Expert
2 days ago
We are seeking a skilled Static Timing Analysis Specialist to lead STA and PNR activities for complex subsystems. This role will focus on robust timing closure, physical implementation, power, performance, and area optimization.
The ideal candidate will have experience in advanced technology nodes (7nm, or below) within ASIC/SoC design. Strong expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) is essential.
This position requires the ability to develop and refine methodologies for STA and PNR tailored to unique challenges of large, multi-interface, or mixed-signal subsystems.
Required Skills and Qualifications- 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR)
- Expertise in STA and PNR tools applied to large, multi-block or hierarchical subsystems
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows
The successful candidate will have the opportunity to work collaboratively across frontend, physical design, and verification teams to integrate complex subsystems. Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level is preferred.
OthersA background in high-speed interfaces or mixed-signal SoC subsystems is highly valued. Excellent communication skills are required to present technical solutions and lead discussions with internal teams and customers.
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