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Senior ASIC Design Professional

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Job Title: Physical Design Expert

As a highly skilled Physical Design Engineer, you will be responsible for leading all aspects of physical design for full-chip and block implementations.

  • Develop and implement efficient floorplanning, placement, budgeting, clock tree planning, and analysis strategies to optimize chip performance.
  • Collaborate closely with the methodology team to resolve implementation challenges and provide valuable insights to improve the physical design flow.
  • Design and develop low-power solutions, leveraging advanced EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, and internal tools.
  • Ensure compliance with design rules, accuracy, and efficiency through thorough EM/IR, DRC, LVS, ERC analysis and fixes.

Key Skills:

  • Expertise in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, and internal tools.
  • Strong hands-on experience with TCL/Perl development skills.
  • Excellent communication and presentation skills, with the ability to effectively collaborate with cross-functional teams.

Requirements:

  • 4+ years of experience in ASIC physical design.
  • Strong understanding of timing constraints, signal integrity prevention, and power reduction techniques.
  • Experience with Synopsys/Cadence/Mentor place and route tools.

Preferred Qualifications:

  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project.
  • Track record of successfully taping out complex chips on advanced process nodes.