
Static Timing Specialist
2 weeks ago
About the Role:
We are seeking an experienced Static Timing Analyst to lead STA and Place and Route (PNR) activities for complex subsystems. This role requires a strong understanding of timing closure, power, performance, and area optimization.
Main Responsibilities:
- Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation.
- Develop and refine methodologies for STA and PNR tailored to unique challenges of large, multi-interface, or mixed-signal subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
- Exhibit excellent communication skills to present technical solutions and lead discussions with internal teams and customers.
Necessary Skills and Qualifications:
- 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design.
- Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus).
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows.
- Deep understanding of SoC design flows and experience collaborating across frontend, physical design, and verification teams.
- Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.
Key Performance Indicators:
- Successfully lead STA and PNR activities for complex subsystems.
- Develop and refine methodologies for STA and PNR.
- Achieve robust timing closure and physical implementation.
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