Design Engineer

8 hours ago


Nellore, Andhra Pradesh, India beBeeStatic Full time ₹ 1,50,00,000 - ₹ 2,02,50,000
Job Title:

Synthesis and Static Timing Analysis

Summary:

Key Responsibilities:
  • Lead full chip and block level timing closure ownership throughout the project cycle.
  • Develop and maintain methodologies related to timing verification and closure.
  • Generate timing constraints for blocks and full chips.
  • Analyze timing reports to drive rapid timing closure.
  • Support digital chip integration work and flows.
Requirements:
  • Expertise in STA tools and methodologies with a good understanding of OCV, noise, and crosstalk effects on timing.
  • Knowledge of timing corners/modes and process variations.
  • Proficient in scripting languages (Tcl and Perl) with knowledge of low-power techniques.
  • Strong communication skills are required to interface with different groups.



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