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Senior Digital Fault Tolerant Architect

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Job Title: Senior DFT Engineer

About the Role:

We are seeking a highly skilled and experienced professional to develop and implement digital fault tolerant (DFT) architectures for ASIC/SoC designs.

Key Responsibilities:

  • Develop and implement DFT architecture for ASIC/SoC designs.
  • Insert and verify scan chains, boundary scan, MBIST, LBIST, and other test structures.
  • Collaborate with RTL and physical design teams to ensure seamless integration of DFT features.
  • Generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.
  • Perform fault simulation and coverage analysis to optimize test quality.
  • Support silicon bring-up and debug of test-related issues.
  • Work with ATE teams to develop test programs and support production testing.

Requirements:

  • 3 years of experience in DFT engineering.
  • Strong knowledge of DFT architecture and implementation.
  • Excellent communication and collaboration skills.
  • Ability to work in a fast-paced environment.

What We Offer:

A competitive compensation package that rewards your skills and expertise.