Senior Digital Fault Tolerance Specialist

9 hours ago


Bengaluru, Karnataka, India beBeeDigitalFaultTolerance Full time ₹ 1,80,00,000 - ₹ 2,40,00,000

Job Role

Experience: 3+ Years

Key Responsibilities:

  • Design and implement digital fault tolerance architectures for complex system-on-chip (SoC) designs.
  • Develop and execute strategies for scan insertion, automatic test pattern generation (ATPG), memory built-in self-test (MBIST), and boundary scan validation.
  • Collaborate with electronic design automation (EDA) vendors to evaluate, deploy, and optimize digital fault tolerance tool flows.
  • Automate repetitive tasks using scripting languages such as Python, Perl, or TCL to improve efficiency and reduce errors.
  • Support test vector generation and validation for automated test equipment (ATE).
  • Provide technical guidance and mentorship to junior engineers in the digital fault tolerance team.

Required Skills:

  • Strong expertise in digital fault tolerance methodologies, including but not limited to: scan insertion & verification, ATPG, MBIST, JTAG / Boundary Scan.
  • Hands-on experience with industry-standard digital fault tolerance tools and methodologies from leading EDA vendors.
  • Proven ability to develop and debug scripting solutions for automation of digital fault tolerance flows.
  • Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.

Preferred Skills:

  • Knowledge of low-power digital fault tolerance techniques.
  • Experience with post-silicon bring-up and ATE patterns.
  • Familiarity with safety-critical standards.
  • Exposure to high-speed IO testing.


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