
Static Timing Analysis Engineer
1 week ago
Job Title: Static Timing Analysis Engineer
Description:
We are seeking a highly skilled and motivated individual to join our implementation team as a Static Timing Analysis (STA) Engineer. This is an excellent opportunity for a professional with expertise in STA to drive performance, power, and area (PPA) optimization and signoff closure.
The successful candidate will be responsible for the RTL-to-GDSII implementation of complex System-on-Chip (SoC) blocks or full-chip designs, utilizing their knowledge of timing closure fundamentals, constraint creation and maintenance, and Digital Fault Tolerance (DFT) modes in STA timing closure.
Responsibilities:
- To lead STA activities for complex SoC designs.
Requirements:
- Bachelor's/Master's degree in Electronics and Communication Engineering, Computer Science Engineering, or related field.
- Minimum 4 years of experience in STA engineering with expertise in timing closure fundamentals, constraint creation and maintenance, and DFT modes in STA timing closure.
We offer a competitive compensation package and opportunities for growth and development in a dynamic environment. Interested candidates can submit their resume at Sharmila.b@acldigital.com.
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