Static Timing Analysis Lead

1 week ago

Hyderabad, Telangana, India beBeeTiming Full time ₹ 80,00,000 - ₹ 1,00,00,000
Job Title: Static Timing Analysis Lead

As a seasoned Static Timing Analyst, you will spearhead STA and PNR activities for complex subsystems, ensuring seamless timing closure and physical implementation with a focus on power, performance, and area optimization.

Key Responsibilities:
  1. Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  2. Drive automation and validation of timing and physical design data across subsystem boundaries.
  3. Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  4. Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
Qualifications and Skills:
  1. 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  2. Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  3. Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  4. Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  5. Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.

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