Senior DFT Strategist

2 days ago

Amrāvati, Maharashtra, India beBeeLeadership Full time ₹ 15,00,000 - ₹ 25,00,000

Lead DFT Engineer Job Opportunity

 

We are seeking a Lead Digital Fault Test (DFT) Engineer to drive the development of digital test and verification methodologies for complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs. This is a challenging position that requires strong technical leadership skills, along with expertise in DFT strategies and architectures.

 

Key Responsibilities:

  • Develop and implement DFT strategies and architectures for multiple ASIC/SoC projects.
  • Design and verify DFT features such as scan insertion and compression, Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), boundary scan, and IEEE 1149.1 Joint Test Action Group (JTAG).
  • Manage end-to-end DFT flows from Register Transfer Level (RTL) to gate-level netlist and silicon bring-up.
  • Collaborate with cross-functional teams including RTL, Static Timing Analysis (STA), Physical Design (PD), and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure, and Automated Test Equipment (ATE) pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior DFT engineers; conduct design reviews and training sessions.

 

Required Skills and Experience:

  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, LBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys DFT Compiler, TetraMAX, TestMAX, Siemens EDA Tessent ScanPro, MBIST, IJTAG, Cadence/others Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.

 

Preferred Qualifications:

  • Experience with hierarchical DFT and low-power DFT methodologies (UPF).
  • Exposure to post-silicon validation and failure analysis.
  • Familiarity with safety-critical designs (ISO 26262) and functional safety.
  • Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).

 

What We Offer:

A competitive compensation package and opportunities for professional growth and development.

 

How to Apply:

Please submit your resume and cover letter to us for consideration.

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