ARM Neoverse System-on-Chip Design Engineer
3 days ago
Our company is seeking a highly skilled engineer to join its team. This role will involve designing IP blocks for ARM Neoverse SoCs, integrating CMN fabric for cache coherence and interconnect.
The successful candidate will have 10+ years of experience in ASIC/FPGA IP/RTL design, with expertise in Verilog/SystemVerilog RTL design and deep knowledge of ARM Neoverse and CMN interconnects.
This role involves designing high-performance, low-latency designs, configuring CMN topologies using Arm Socrates for optimized performance and scalability, and implementing protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
Key responsibilities include:
- Designing IP blocks for ARM Neoverse SoCs, integrating CMN fabric for cache coherence and interconnect
- Developing Verilog/SystemVerilog RTL for high-performance, low-latency designs
- Configuring CMN topologies using Arm Socrates for optimized performance and scalability
- Implementing protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects
- Optimizing designs for bandwidth, latency, and power in AI/HPC workloads
Additionally, you will support synthesis, timing closure, and FPGA prototyping and Design Verification team, and document microarchitecture and design specifications.
Our team offers a collaborative environment where you can work with exceptional engineers who come from the top companies in the semiconductor industry.
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