High-Performance System-on-Chip Architect
3 days ago
As a Principal IP/RTL Design Engineer, you will play a key role in shaping the future of technology.
We are seeking an experienced professional to design IP blocks for ARM Neoverse SoCs, integrating CMN fabric for cache coherence and interconnect.
Key Responsibilities:
- Design high-performance, low-latency designs using Verilog/SystemVerilog RTL.
- Configure CMN topologies for optimized performance and scalability using Arm Socrates.
- Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
- Optimize designs for bandwidth, latency, and power in AI/HPC workloads.
- Support synthesis, timing closure, and FPGA prototyping and Design Verification team.
- Document microarchitecture and design specifications.
To be successful in this role, you must have:
- Bachelor's/Master's/Ph.D. in Electronics/Computer Engineering.
- 10+ years of experience in ASIC/FPGA IP/RTL design.
- 5+ years of experience with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3).
- Expertise in Verilog/SystemVerilog RTL design.
- Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects.
- Experience with Arm Socrates for CMN configuration.
- Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols.
- Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler).
- Experience with AI/HPC or datacenter SoC design.
- Knowledge of DDR5, HBM3, or chiplet-based architectures.
- Familiarity with UALink or Ultra Ethernet.
- Strong problem-solving and collaboration skills.
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