Chief Innovation Architect

19 hours ago

Greater Hyderabad Area, India beBeeChip Full time US$ 15,00,000 - US$ 18,00,000

Job Overview:

We are seeking a seasoned Senior Chip Lead to spearhead the development of cutting-edge devices.

About the Role:

This is a critical leadership position that demands strategic thinking, technical expertise, and exceptional collaboration skills. As a Senior Chip Lead, you will be responsible for driving full chip design, ensuring seamless integration with architect and design teams, and making key decisions on Performance, Power, and Area (PPA).

  • Develop a comprehensive project plan, defining multiple checkpoints for IP, SoC Design, DV, and PD teams.
  • Collaborate with Analog/Digital IP teams to integrate IPs and drive full chip floorplan and bump maps.
  • Establish sign-off criteria, guaranteeing high-quality standards and thorough testing.
  • Define RTL Quality gate criteria, including lint, CDC, and essential checks.
  • Drive timing constraints/timing analysis/closure activities, achieving efficient results.
  • Define DFT targets and work with Physical Design engineers to achieve physical design closure.
  • Ensure smooth project completion by handling tapeout formalities.

Key Qualifications:

  • Minimum 15 years of solid experience in SoC design.
  • A self-starter who can define things where none exist.
  • Possesses proven ability to develop architecture and micro-architecture from specifications.
  • Strong understanding of chip I/O design and packaging is beneficial.
  • Experience in reviewing top-level test plans and expertise in Synopsys Design Compiler for synthesis and formal verification.
  • Knowledge of design verification aspects is essential.
  • Demonstrated expertise in specific technical areas, with significant experience in related fields.
  • Proven leadership skills, with the ability to provide direction, mentoring, and guidance to small to medium-sized teams.

Fundamental Skills:

  • Excellent communication and leadership skills.
  • Able to make timely and effective decisions, even with incomplete information.
  • Strong working knowledge of timing closure processes and post-silicon bring-up and debugging.
  • Familiarity with SoC integration challenges and commercialization process.

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