ARM Neoverse Lead Designer Position
22 hours ago
Lead ARM Neoverse IP/RTL Design Expert
- We are seeking an accomplished Principal IP/RTL Design Engineer to spearhead the design of high-performance, low-latency IP blocks for ARM Neoverse-based SoCs integrating CMN fabric.
Main Responsibilities:
- Design high-bandwidth, low-latency IP blocks for ARM Neoverse SoCs integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect.
- Develop Verilog/SystemVerilog RTL designs optimizing for bandwidth, latency, and power in AI/HPC workloads.
- Configure CMN topologies using Arm Socrates for optimized performance and scalability.
- Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
- Support synthesis, timing closure, and FPGA prototyping.
- Document microarchitecture and design specifications.
Required Skills and Qualifications:
- Bachelor's/Master's/PhD degree in Electronics/Computer Engineering.
- 10+ years of experience in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics.
- Expertise in Verilog/SystemVerilog RTL design.
- Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects.
- Experience with Arm Socrates for CMN configuration.
- Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols.
- Familiarity with synthesis and timing tools.
- Experience with AI/HPC or datacenter SoC design.
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