Senior High-Performance IP Designer for Next-Generation Datacenter Systems
5 days ago
We are seeking a skilled Design Engineer with 10+ years of experience to design high-performance, low-latency IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications.
The ideal candidate will have expertise in Verilog/SystemVerilog RTL design, deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects, and experience with Arm Socrates for CMN configuration.
Key Responsibilities:- Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect.
- Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs.
- Configure CMN topologies using Arm Socrates for optimized performance and scalability.
- Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects.
- Optimize designs for bandwidth, latency, and power in AI/HPC workloads.
- Education: BS/MS/PhD in Electronics/Computer Engineering.
- Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3).
- Skills:
- Expert in Verilog/SystemVerilog RTL design.
- Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects.
- Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols.
- Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler).
- Experience with AI/HPC or datacenter SoC design.
- A meritocracy-first workplace where each peer is a star.
- A chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world.
- A pure-play product work environment.
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