Senior Digital Testing Professional

3 days ago

Ajmer, Rajasthan, India beBeeDftEngineer Full time ₹ 1,00,00,000 - ₹ 2,00,00,000

Job Title:

Digital Fault Test Engineer

Experience: 4 to 12 years in ASIC/DFT - simulation and Silicon validation

Location: India

Key Responsibilities:

  • Collaborate with cross-functional teams to implement DFT design rules and coverages.
  • Create high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques.
  • Perform MBIST verification, including repair, and test pattern generation using Mentor tools.
  • Conduct ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
  • Work with Product/Test engineering teams on manufacturing test pattern delivery for ATE.
  • Solve post-silicon debug issues and resolve them.
  • Develop diagnostic tools for ATPG, MBIST, and ATE bring-up.
  • Maintain and enhance scripts as necessary.

Preferred Experience:

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering.
  • Minimum of 4 to 12 years' experience in ASIC/DFT simulation and Silicon validation.
  • Work experience in at least one full chip DFT project.
  • In-depth knowledge of DFT concepts, pattern simulation, Silicon debug, and yield enhancement.
  • Familiarity with ATPG - coverage analysis.
  • Expertise in Memory verification, repair, and failure root-cause analysis.
  • Experience with tools like TestKompress, ETVerify, VCS, and ModelSim is required.
  • Proficiency in scripting languages such as Perl and shell is an added advantage.
  • Good communication skills and ability to work in a dynamic environment.
  • Ability to learn new tools and methodologies.
  • Multi-tasking skills and ability to work on several high-priority designs simultaneously.

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