High Performance On-Chip Interconnect Design Lead

1 day ago

Udaipur, Rajasthan, India beBeeHardware Full time US$ 1,50,000 - US$ 2,50,000
Job Description

As a leader in hardware design, you will be responsible for architecting and developing high-performance on-chip interconnects (NoC) and chip-to-chip interconnects.

This role involves designing various interconnect topologies to meet bandwidth, latency, and reliability requirements. You will also develop micro-architectures, create RTL designs, and collaborate with verification, DFT, physical design, FW, and SW teams to implement features.

  • Develop and present proposed architectures in high-level design discussions.
  • Design and architect different interconnect topologies as driven by bandwidth, latency, and RAS requirements.
  • Sign off pre-silicon designs that meet all functional, area, and timing goals.
Key Responsibilities:
  • Lead the design of high-bandwidth, low-latency on-chip interconnects and chip-to-chip interconnects.
  • Collaborate with cross-functional teams to implement feature enhancements.
  • Participate in silicon bring-up and validation of the hardware.
Preferred Qualifications:
  • 8+ years of relevant experience.
  • Expertise in at least one generation of processor interconnect design delivery leadership.
  • Strong understanding of SMP coherency, numa/nuca architecture, and queuing theory.
What We Offer:
  • Opportunities for career growth and professional development.
  • A collaborative and dynamic work environment.

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