Leading Edge Chip Designer

6 days ago

Udaipur, Rajasthan, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,00,00,000

Objective

Physical Design Engineer

Seeking a skilled Physical Design Engineer for a critical role in our organization.

This position is responsible for all aspects of physical design, including floorplanning, placement, budgeting, clock tree planning & analysis, scan re-ordering, clock tree synthesis, placement optimizations, routing, timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation.

The ideal candidate will have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.

  • Work closely with the methodology team to solve implementation challenges & provide inputs to improve the physical design flow.
  • Experience in design automation is required.
  • Understanding of timing constraints, SI prevention, power reduction is necessary.
  • Prior experience with Synopsys/Cadence/Mentor place and route tools is a must.
  • The ability to proficiently use Unix/TCL/Perl is essential.

Requirements

  • 4+ years experience in ASIC physical design is required.
  • Experience with block implementation, extraction, timing, and or full-chip designs is necessary.
  • Strong communication skills are required.
  • Strong hands-on TCL/Perl development skills are necessary.

Preferred Qualifications

  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project is preferred.
  • A track record of taping out complex chips on advanced process nodes is desired.

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