Expert SoC Design Engineer

2 days ago


Udaipur, Rajasthan, India beBeeEngineering Full time ₹ 80,00,000 - ₹ 2,00,00,000

We are seeking an experienced Static Timing Analysis (STA) Engineer to implement complex System-on-Chip (SoC) blocks or full-chip designs from Register Transfer Level (RTL)-to-Goodspeed Intermediate Format (GDSII), targeting performance, power, and area (PPA) optimization and signoff closure.

Key Responsibilities:
  • Timing Closure Fundamentals
  • Constraint Creation and Maintenance Exposure
  • Design for Testability (DFT) Modes in STA Timing Closure

In this role, you will collaborate closely with cross-functional teams to develop innovative solutions that meet the demands of modern semiconductor design. Your strong background in STA engineering and passion for delivering high-quality results make you a great fit for this opportunity.

About the Opportunity: This is a key position in our backend implementation team, responsible for implementing complex SoC blocks or full-chip designs.



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