Senior Design Engineer for Advanced Mixed-Signal Chip Synthesis and Timing Analysis

1 week ago

Kurnool, Andhra Pradesh, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,50,00,000
Senior Design Engineer for Advanced Mixed-Signal Chip Synthesis and Timing Analysis

We are seeking an experienced Senior Design Engineer to lead the synthesis and static timing analysis efforts for an advanced mixed-signal chip. This role involves full chip and block-level timing closure ownership throughout the project cycle, from RTL to physical implementation.

The ideal candidate will have a strong background in ASIC timing constraints generation and timing closure, with expertise in STA tools like Tempus and Primetime. Experience with low-power techniques, including clock gating, power gating, and millivoltage designs, is also essential.

This position requires a deep understanding of timing corners/modes and process variations, as well as knowledge of scripting languages like Tcl and Perl. The successful candidate will be able to analyze timing reports, develop insights, and drive rapid timing closure.

Main Responsibilities:
  • Full chip and block-level timing closure ownership throughout the project cycle (RTL, synthesis, and physical implementation).
  • Develop and maintain methodology and flows related to timing verification and closure.
  • Generation of block and full-chip timing constraints.
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
Required Skills and Qualifications:
  • B.Tech/M.Tech/Ph.D. with at least 6+ years of hands-on experience in ASIC timing constraints generation and timing closure.
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
  • Knowledge of timing corners/modes and process variations.
  • Knowledge of low-power techniques, including clock gating, power gating, and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
Benefits:

This role offers opportunities for career growth and development, as well as a chance to work on cutting-edge projects with top industry leaders. Our team provides a collaborative and supportive environment, with a focus on delivering high-quality results.

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