Senior ASIC Design Engineer

4 days ago

Kurnool, Andhra Pradesh, India beBeeDesign Full time ₹ 1,50,00,000 - ₹ 2,00,00,000

Job Role: Senior ASIC Design Engineer - Physical Design

Overview:

Our team is seeking an experienced Senior ASIC Design Engineer to lead our physical design efforts, driving innovation and excellence in the development of cutting-edge semiconductor products. As a key member of our team, you will be responsible for overseeing all aspects of physical design, from floorplanning and placement to budgeting, clock tree planning and analysis, routing, timing, and signal integrity (SI) analysis.

You will work closely with our methodology team to identify implementation challenges and develop solutions to improve our physical design flow. Your expertise in EDA tools, such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, and Calibre, will be crucial in achieving success in this role.

In addition to your technical skills, you will also have excellent communication and presentation skills, enabling you to effectively collaborate with cross-functional teams and stakeholders. Strong interpersonal skills and problem-solving abilities are essential for this position.

Key Responsibilities:

  • Lead all aspects of physical design, including floorplanning, placement, budgeting, clock tree planning and analysis, routing, timing, and SI analysis;
  • Collaborate with the methodology team to develop solutions for implementation challenges and improve the physical design flow;
  • Work with EDA tools, such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, and Calibre;
  • Provide expert guidance on design automation, low-power solution development, and EM/IR analysis and fixes;
  • Manage and deliver projects on time and within budget;

Requirements:

  • 4+ years of experience in ASIC physical design;
  • Experience with block implementation, extraction, timing, and full-chip designs;
  • Strong hands-on skills in TCL/Perl development;
  • Strong communication and presentation skills;
  • Proficient in Unix/TCL/Perl;
  • Good interpersonal and problem-solving skills;
  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project;
  • Track record of taping out complex chips on advanced process nodes;

We offer a dynamic work environment, opportunities for growth and professional development, and a competitive compensation package.

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