Senior Design Verification Engineer

Design Verification Engineer (7-10 years' experience)

Company: HCL Tech

Job Summary:

We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.

Responsibilities:

• Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
• Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage
• Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality
• Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
• Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
• Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment
• Participate in code reviews and champion best practices for verification code quality
• Stay current with the latest advancements in verification tools and methodologies

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
• 7-10 years of solid experience in Design Verification for ASICs or SoCs
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to develop, debug, and optimize complex verification environments
• Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
• Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
• Experience with formal verification tools and techniques is a plus
• Excellent analytical and problem-solving skills with a meticulous attention to detail
• Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

Benefits:

• Competitive salary and benefits package commensurate with experience
• Opportunity to work on leading-edge technologies and projects with a high impact
• Collaborative and dynamic work environment that fosters continuous learning
• Potential for professional development and career advancement

Design Verification Engineer (Senior Level - 10+ years' experience)

Company: HCL Tech

Job Summary:

We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies.

Responsibilities:

• Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification)
• Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals
• Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis
• Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution
• Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team
• Champion best practices for verification code quality and participate in code reviews
• Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies
• Provide technical leadership and contribute to the overall verification roadmap for the team

Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
• Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs
• Proven track record of successfully leading and executing verification projects
• In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices
• Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques
• Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages)
• Excellent leadership, communication, collaboration, and problem-solving skills
• Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines

Benefits:

• Competitive salary and benefits package commensurate with experience and expertise
• Opportunity to lead and influence the verification of cutting-edge technologies
• Dynamic and challenging work environment with opportunities for professional growth and leadership development
• Recognition and rewards for outstanding contributions