Senior ASIC Timing Closure Specialist

2 weeks ago

Kurnool, Andhra Pradesh, India beBeeEngineer Full time ₹ 20,00,000 - ₹ 25,00,000

About Synthesis and Static Timing Analysis

We are looking for a highly skilled and experienced ASIC STA Engineer to join our team. As a key member of our digital design team, you will be responsible for providing integrated solutions for advanced mixed signal chips.

The ideal candidate will have thorough knowledge of the ASIC design timing closure flow and methodology. They will be able to generate block and full chip timing constraints, analyze timing reports, and utilize scripting techniques to develop insights and drive rapid timing closure.

Key qualifications include BTech/MTech/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure, expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing, familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm, knowledge of timing corners/modes and process variations, and proficiency in scripting languages (Tcl and Perl).

Responsibilities:
  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
  • Develop and maintain methodology and flows related to timing verification and closure
  • Generation of block and full chip timing constraints
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid Eteros Technologies, Inc. Confidential Sep 2020 timing closure
Requirements:
  • Bachelor's or Master's degree in Electronics Engineering or Computer Science
  • At least 6+ years hands-on experience in ASIC timing constraints generation and timing closure
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm
  • Knowledge of timing corners/modes and process variations
  • Proficiency in scripting languages (Tcl and Perl)
What We Offer:
  • A competitive compensation package
  • Medical benefits
  • A dynamic and collaborative work environment

This is an excellent opportunity for a motivated and experienced professional to join our team and contribute to the development of cutting-edge technologies.

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