
Test Architect
9 hours ago
We are seeking a skilled Test Architect to drive the development of complex System-on-Chip (SoC) designs. This role will involve defining and implementing DFT architectures, as well as planning, executing, and delivering scan, ATPG, MBIST, and boundary scan insertion and validation.
The successful candidate will have strong expertise in DFT architectures and methodologies, with hands-on experience with industry-standard DFT tools from Cadence, Synopsys, and Mentor Graphics (Siemens EDA). Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows is essential.
Key Responsibilities:
- Drive DFT architecture definition and implementation for complex SoCs.
- Plan, execute, and deliver scan, ATPG, MBIST, and boundary scan insertion and validation.
- Work with EDA vendors to evaluate, deploy, and optimize DFT tool flows.
- Automate repetitive tasks using scripting to improve efficiency and reduce errors.
- Support test vector generation and validation for ATE.
- Strong expertise in DFT architectures and methodologies.
- Hands-on experience with industry-standard DFT tools from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).
- Proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
- Solid understanding of SoC design cycle, RTL to GDSII flow, and test requirements.
- Competitive salary and benefits package.
- Opportunities for career growth and professional development.
- Collaborative and dynamic work environment.
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