Senior DFT Architect

2 days ago

Meerut, Uttar Pradesh, India beBeeDigitalFaultTolerance Full time ₹ 20,00,000 - ₹ 25,00,000
Job Title: Lead DFT Engineer

We are seeking an experienced technical lead to drive the development of Digital Fault Tolerance (DFT) architecture, planning, and implementation across complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs.

This technical leader will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products. Key responsibilities include defining and driving DFT strategy and architecture for multiple ASIC/SoC projects.

  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Lead implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
  • Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
Required Skills and Qualifications
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.

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