
Senior ASIC Design Engineer for Complex SoC Projects
4 days ago
Job Title: Senior ASIC Design Engineer for Complex SoC Projects
Key Responsibilities:
- Develop and drive DFT strategies for multiple ASIC/SoC projects.
- Lead the implementation and verification of DFT features including scan insertion, ATPG pattern generation, fault grading, MBIST, Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
- Manage the end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
- Collaborate with cross-functional teams for seamless integration.
- Perform pattern generation, fault simulation, and debug test coverage gaps.
Required Skills and Experience:
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
- 8+ years of experience in DFT for complex ASIC or SoC designs.
- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
- Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence/others.
- Strong knowledge of RTL design, STA, and synthesis flows.
- Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
Preferred Qualifications:
- Experience with hierarchical DFT and low-power DFT methodologies (UPF).
- Exposure to post-silicon validation and failure analysis.
- Familiarity with safety-critical designs (ISO 26262) and functional safety.
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