
Principal ASIC Design Verification Expert
3 days ago
We are seeking an accomplished Design Verification Engineer to play a key role in ensuring the quality and functionality of our advanced ASICs.
- Develop comprehensive verification plans utilizing industry-leading methodologies like UVM and Formal Verification.
- Create high-quality verification environments (testbenches) for exceptional code coverage.
- Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality.
- Debug and analyze verification failures with attention to detail to identify and resolve design issues.
- Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence.
- Lead and mentor junior DV engineers within the team, promoting knowledge sharing and collaboration.
Responsibilities:
- Develop comprehensive verification plans utilizing industry-leading methodologies like UVM and Formal Verification.
- Design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals.
- Utilize industry-leading verification tools (simulators, formal verification tools) for thorough verification and analysis.
- Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution.
- Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team.
- Champion best practices for verification code quality and participate in code reviews.
- Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies.
Requirements:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus).
- 7-10 years of experience in Design Verification for ASICs.
- In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines).
- Proven ability to develop, debug, and optimize complex verification environments.
- Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal).
- Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl).
- Experience with formal verification tools and techniques is a plus.
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