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2 days ago
MosChip is a leading semiconductor and embedded system design company.
Key Responsibilities:- Provide technical guidance to engineers in physical design.
- Interface with front-end ASIC teams to resolve issues.
- Develop low-power solutions using voltage islands, power gating, and substrate-bias techniques.
- Ensure timing closure on DDR2/DDR3/PCIE interfaces.
- Implement robust physical verification methodologies.
For success in this role, you will need extensive experience with Cadence or Synopsys or Magma physical design tools, scripting languages like PERL and TCL, and static timing analysis in Primetime or Primetime-SI. A strong background in ASIC physical design, floor planning, P&R, extraction, IR Drop Analysis, Timing, and Signal Integrity closure is essential.
Requirements:The ideal candidate will possess excellent knowledge of the following:
- Cadence or Synopsys or Magma physical design tools
- Scripting languages (PERL, TCL)
- Static timing analysis (Primetime, Primetime-SI)
A strong background in ASIC physical design, floor planning, placement and routing (P&R), extraction, IR drop analysis, timing, and signal integrity closure is crucial for this position.
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