
Lead ASIC Physical Designer
4 days ago
We are seeking a seasoned Senior Physical Design Engineer to join our team.
Key Responsibilities
- We require an experienced engineer with a strong background in ASIC Physical Design, Floor planning, Partitioning and placement, Routing and signal integrity closure.
- The ideal candidate should have extensive experience working on 65nm or lower node designs using advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias.
- You will be responsible for providing technical guidance and mentoring to junior Physical Design Engineers.
- We need someone who can interface effectively with front-end ASIC teams to resolve issues and drive project forward.
- Achieving timing closure on DDR2/DDR3/PCIE interfaces is also a key requirement.
- You will collaborate closely with cross-functional teams to deliver projects on time.
Requirements
- Strong background in ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
- Extensive experience in Cadence or Synopsys or Magma physical Design Tools.
- Expertise in scripting languages such as PERL, TCL.
- Strong Physical Verification skill set.
- Familiarity with Static Timing Analysis in Primetime or Primetime-SI.
- Excellent written and oral communication skills. Ability to clearly document plans.
- Ability to interface with different teams and prioritize work based on project needs.
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